Nonvolatile data storage is commonly used in integrated circuits. Conventional nonvolatile transistor memory cells commonly include a polysilicon floating gate formed over a tunnel dielectric over a semiconductor substrate as a charge storage region. Some types of semiconductive devices for nonvolatile data storage use isolated nanocrystals (also referred to as nanoparticles) to replace the floating gate as a charge storage area. Charge is transferred through the tunnel dielectric (also referred to as tunnel oxide) to the nanocrystal layer. The electrostatic properties of the nanocrystal layer are modified, which influences a subsurface channel region between source and drain in a MOS transistor to represent various logical values. The charge capturing capability of the nanocrystals is affected by the density, size and distribution of the nanocrystals. The nanocrystals are distributed over the channel region and should be capable of holding a sufficient charge. Too few nanocrystals may not be able to control the channel.
In order to have a significant memory effect, it is necessary to have a high density of nanocrystals forming the charge storage regions. Current methods form nanocrystals using, for example, a chemical vapor deposition (CVD) technique to deposit a semiconductor material over a substrate. The material is then annealed to form the nanocrystals.
As the size of semiconductor devices scale down to 40 nm and beyond, the number of nanocrystals per bit cell dwindles. Consequently, with ever shrinking devices, nanocrystal distribution in a charge storage area increasingly impacts bit cell performance and reliability. To extend current nanocrystal technology to the next node as a storage source, formation of a required density of nanocrystals within a bit cell, particularly in conjunction with the channel region of a control gate or memory gate, is desired.